1 LD4200 newport advance information features general 100 - 550 mb/sec data rate operation extended class 4 pa rtial response with viterb i detection (eprml) system rate 16/17 trellis constraint code ( 32/34 endec ) with post-processor robust frame synchronization support okc dual sync byte and tco direct write with lv diff input code violation flag programmable continuous-time + adaptive boost equalization programmable write precompensation thermal asperity detection and compensation for mr heads adaptive compensation for mr head amplitude asymmetry 3 taps cosine equalizer 8-bit nrz interface 3-wire serial port for parameter and mode control 3.3v ( 5%) power supply power management less than 15 mw during power down mode 0.25 m technology equalization 7-th order equiripple con tinuous-time filter with prog rammable cut-off frequency, boost, and asymmetry of zeros. on-chip functions to assist in the selection of the filter parameters for equalization to epr4 target pulse response. adaptive boost control for equalizing amplitude distortion. automatic gain control decision-directed digital ac quisition and tracking loops. fixed gain mode with programmable ga in range of 0.25 to 4.0 using 8-bit dac. steps are equally spaced in 0.1 db/lsb. two additional gain range se ttings: low gain mode decreases the gain range by 4.5db. high gain mode increases the gain range by 4 db. programmable viterbi gain with values from 1-6/32 to 1+6/32 in 1/32 steps. timing recovery decision-directed digital timing recovery for both acquisition and tracking modes. zero phase startup for rapid acquisition. ml detector 8-state viterbi detector for epr4 target response. marginalized data available for use in margin-type (stress) testing.
2 LD4200 newport advance information data separator robust frame synchronizati on. programmable time-out and programmable error tolerance on sync byte detect. single byte sync byte indicator. 100 to 550 mb/sec operation. frequency synthesizer independent ?divide-by? registers for refe rence frequency and vco output frequency. 10 to 60 mhz reference clock. 3-to-1 range with better than 1% resolution. write mode preamble is written immediately after activation of write gate (wg) (active high). cia write mode: writes the preamble, sync byte, and prbs pattern. immediate direct write mode: bypass pream ble, sync byte, encoder and precoder. programmable precompensation of up to 35% of the write bit interval in approximately 1.13% steps to compensa te for transition-shift distortion. squelch vga input during write mode (agc is held). squelch duration after deactivation of wg is programmable usin g wgdly(register ta2, 0x7c[7:5]) from 0 to 56*tfref1 sec steps ( tfref1 = one period or half period of fref clock). read mode cia read mode: bypass decoder and precoder. pipeline read feature. adaptive compensation of mr head amplitude asymmetry. adaptive compensation of dc offset in adc. thermal asperity detection/correction . on-chip programmable noise generator to accelerate bit error rate tests . channel integration assist (cia) sum-of-squared error output register for measuring signal quality and selecting equalizer parameter settings. register is reset after each fetch. surface defect scan with provision for defining separate positive and negative amplitude qualification thresholds. frequency indicator for vco center frequency calibration. on chip ber capability. servo asynchronous digital servo
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